Graduate Students (Dissertation or Thesis)

• Azam Beg, Ph.D., Aug. 2005, Assistant Professor at the College of Information Technology, United Arab Emirate University.
  Ph.D. Dissertation: Improving Instruction Fetch Rate with Code Pattern Cache for Superscalar Architecture [PDF]
• Rami Ammari, May 2004, H/W Engineer, Sun Microsystems
  MS Thesis: A Study for Reducing Conflict Misses in Data Cache [PDF]
• Vinod Rajan, MS, Dec. 2004, Design Engineer, Cypress Semiconductors
  MS Thesis: An Enhanced Dynamic Algorithm for Packet Buffer [PDF]
• Arul Sandeep Gade, MS, May 2005, Component Design Engineer, Intel
  MS Thesis: A Dual-Port Data Cache with Pseudo-Direct Mapping Function [PDF]
• Saibhushan Musalappa, M.S., December 2006 (Defended in July 2006)
  MS Thesis: An Energy Efficient data Cache Implementing 2-Way LRC Architecture [PDF]
• Shalini Batra, M.S., August 2007 (Defended in May 2007)
  MS Thesis: An Efficient Algorithm and Architecture for Network Processors [PDF]

• Amit Uppal, M.S., December 2007 (Defended in October 2007) [PDF]
  MS Thesis: Increasing the Efficiency of Network Interface Card

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Referred Journal & Conference Proceedings

     Journals (published or accepted):

• Azam Beg and Yul Chu, "Modeling of Trace- and Block-Based Caches," Journal of Circuit, Systems, and Computers (JCSC), World Scientific, 2008 (in press)  

• Jin H. Park and Yul Chu, "FSM-based DRAM Power Management with Early Resynchronization," IET (IEE) Computers and Digital Techniques, Volume 1, issue 4, pp. 434-442, July 2007.[PDF]
• Azam Beg and Yul Chu," Utilizing Block Size Variability to Enhance Instruction Fetch Rate," Journal of Computer Science and Technology, Springer, Volume 7, No.2, pp. 155-161, April 2007.[PDF] 
• BAE Chul-Ho, CHU Yul, KIM Hyun-Jun, LEE Jung-Hwan, SUH Myung-Won, "A Study on Maintenance Reliability Allocation of Urban Transit Brake System using Hybrid Neuro-Genetic Technique," International Journal of Mechanical Science and Technology, Vol. 21, No.1, pp. 32-47, 2007. Impact factor: 0.44.
• Yul Chu, "A Class Project for Low-Power Cache Memory Architecture," Computers in Education Journal, Computers in Education Division of ASEE, 2006 (accepted) 
• Yan Bai, Yul Chu, M. R. Ito, "Joint QoS Distribution and Packet Scheduling for Streaming Video Using Active Networks," Elsevier International Journal of Electronics and Communications, accepted subject to revision, 2006.
• Yul Chu, Arul S. Gade, and Abhishek Bhaduri, "A Low-Power Cache Scheme of Embedded Computing," Special issue on Embedded Single-Chip Multicore Architectures and related research, from System Design to Application Support, Journal of Embedded Computing, IOS Press, Issue 2, No. 2, pp. 261-269, 2006. [PDF]
• Yul Chu, "A Simple Project Paradigm for Teaching Computer Architecture," Computers in Education Journal, Computers in Education Division of ASEE VOL. XVI No.2, pp. 106-112, April-June 2006. [PDF]
• K. Y. Cho, C. H. Bae, Y. Chu, and M. W. Suh, "An Overview of Telematics: A System Architecture Approach," International Journal of Automotive Technology, Vol. 7, No. 4, pp. 509-517, 2006. Impact factor: 0.90 [PDF]
• K.Y. Cho, C.H. Bae, J.H. Lee, Y. Chu, and M.W. Suh, "The Integrated Control Model for the Freeway Corridors based on Multi-Agent Approach II: Optimization using Neural Network and Simulated Annealing Method," Transactions of the Korean Society of Automotive Engineers, Vol. 14, No. 5, pp. 84-92, 2006.
• K. Y. Cho, C. H. Bae, H.J. Kim, Y. Chu, and M. W. Suh, "The Integrated Control Model for the Freeway Corridors based on Multi-Agent Approach I: Simulation System & Modeling for Optimization," Transactions of the Korean Society of Automotive Engineers, 2006 (accepted, to appear).
• C. H. Bae, Yul Chu, H. J. Kim, T. Y. Koo, and M. W. Suh, "A study on the Development of a web based Urban Transit Reliability Evaluation System," International Journal of Information Systems and Change Management, 2006 (accepted, to appear). Impact factor: 0.44
• Ausif Mahmood, Yul Chu, and T. Sobh, "Parallel Sparse-Matrix Solution for Direct Circuit Simulation on a Transputer Array ," IEE Journal on Circuits, Devices and Systems,  vol. 144, no. 6, pp. 335-342, 1997.[PDF]

  Proceedings (published or accepted):

•  Shalini Batra, Yul Chu, and Yan Bai, "Packet Buffer Management for a High-Speed Network Interface Card," in the proceedings of 16th IEEE International Conference on Computer Communications and Networks (ICCCN 2007), Honolulu, Hawaii USA, August 13-16, 2007 (acceptance rate: 29%). [PDF]  
• Amit Uppal and Yul Chu, "A Dynamic Packet Buffer in a Network Interface Card," accepted by the IEEE International Conference on Systems and Networks Communications (ICSNC 2006), Tahiti Polynesia, November 2-4, 2006 (acceptance rate: 32%, 85/267).
• Amit Uppal and Yul Chu, "A Shared-Memory Packet Buffer Management," the 9^th Asia-Pacific Network Operations and Management Symposium (APNOMS 2006), Proceedings of the LNCS 3894, pp 517-520, Busan, Korea, September 27-29, 2006 (acceptance rate: 34%, 75/220).
• Arul S. Gade and Yul Chu, "A Case for Dual-Mapping One-Way Caches," IEEE/ACM/IFIP Architecture of Computing Systems (ARCS'06), Proceedings of the LNCS 3894, pp.130-144, Frankfurt/Main, Germany, March 13-16, 2006 (acceptance rate: 18%, 32/174).
• Yul Chu, "A Class Project for Low-Power Cache Memory Architecture," 2006 ASEE Annual Conference & Exposition, Computers in Education Division [CD-ROM], Chicago, IL, June 18-21, 2006.
• Vinod Rajan and Yul Chu, "An Enhanced Dynamic Packet Buffer management," in the proceedings of the 10^th IEEE Symposium on Computers and Communications (ISCC 2005), pp. 869-874, La Manga del Mar Menor, Cartagena, Spain, June 27-30, 2005 (acceptance rate: 36%, 147/400).[PDF]
• Tieling Xie, Yul Chu, and Jin Hwan Park, "Approaches to Improve Performance for History-Based Branch Predictors," in the proceedings of IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing (PACRIM'05), pp. 121-124, Victoria, B.C., Canada, August 24-26, 2005.
•  Azam Beg and Yul Chu, "Improved Instruction Fetching with a New Block-Based Cache Scheme," in the proceedings of the IEEE International Symposium on Signals, Circuits & Systems (ISSCS 2005), lasi, Romania, July 14-15, 2005.
• Yul Chu, "A DCT (Design, Code, Test) Project for Instruction Set Architecture," in the proceedings of the 5^th IEEE International Conference on Advanced Learning Technologies (ICALT 2005), pp. 69-71, Kaohsiung, Taiwan, July 5-8, 2005.
• Srinivas K. Damodara and Yul Chu, "A Study for a Dynamic Target-Prefetching Scheme," in the proceedings of the 2005 International Conference on Parallel and Distributed Processing techniques and Applications (PDPTA'05), pp. 1149-1155, Las Vegas, Nevada, USA, June 27-30, 2005.
• Saibhushan Musalappa, Shivakumar Sundaram, Yul Chu, "A Low Power Cache for Embedded Processors," accepted by the 8^th IEEE International Symposium on Low-Power and High-Speed Chips (CoolChips VIII), Yokohama, Japan, April 20-22, 2005.
• Vinod Rajan and Yul Chu, "A Study for Packet Buffer Algorithms for the Protocol Processor," in the proceedings of the 3^rd IEEE International Conference on Information Technology and Applications (ICITA'2005) [CD-ROM], pp. Sydney, Australia, July 4-7, 2005.
•  Saibhushan Musalappa, Shivakumar Sundaram, Yul Chu, "A Replacement Policy to Save Energy for Data Cache," in the proceedings of the 19^th IEEE International Symposium on High Performance Computing Systems and Applications (HPCS 2005), pp. 72-75, Guelph, Canada, May 15-18, 2005.
• Tieling Xie, Robert Evans, and Yul Chu, "A Study for Branch Predictors to Alleviate the Aliasing Problem," Proceedings of the IEEE SoutheastCon 2005, pp. 603-608, Fort Lauderdale, Florida, USA, April 8-10, 2005.[PDF]
• Saibhushan Musalappa, Shivakumar Sundaram, Yul Chu, "An Energy-Efficient Replacement Policy for Data Cache," Proceedings of the IEEE SoutheastCon 2005, pp. 599-602, Fort Lauderdale, Florida, USA, April 8-10, 2005.
• Yan Bai, Yul Chu, M. R. Ito, "Intelligent Packet Discard and Active Node Architecture for Video Delivery," accepted by the 7^th International Conference on Advanced Communication Technology (ICACT), Phoenix Park, Korea, February 2005.
• Yul Chu and M. R. Ito, "An Efficient Indirect Branch Predictor ," ACM European Conference on Parallel Computing (Euro-Par 2001), Manchester, United Kingdom, August 2001.[PDF]
• Yul Chu and M. R. Ito, "A New Instruction Cache Scheme for Object-Oriented Languages ," in the proceedings of the 20^th IEEE International Performance, Computing, and Communications Conference (IPCCC2001), Phoenix, Arizona, April 2001.[PDF]
•  Yul Chu and M. R. Ito, " The 2-way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented Languages ," in the proceedings of the 17^th IEEE International Conference on Computer Design (ICCD2000), Austin, Texas, September 2000.[PDF]
• Yul Chu and M. R. Ito, "The GoStay Predictor: One-Bit Associated Predictor for Reducing Indirect Branch Mispredictions," the 14^th Annual International Symposium on High Performance Computing Systems and Applications (HPCS2000), Victoria, Canada, June 2000.
• Yul Chu and M. R. Ito, "Thrash Avoidable Cache (TAC) for Reducing Instruction Cache Misses," the 6^th IEEE International Symposium on High-Performance Computer Architecture WIP session, Toulouse, France, January 2000. This paper was also accepted in the IEEE TCCA newsletter.
• Yul Chu, Ausif Mahmood, and Donald J. Lynch, "Parallelization of Solve in Direct Circuit Simulation on a Transputer Array ," in the proceedings of the third IEEE International Conference on High Performance Computing (HiPC'96), Trivandrum, India, December 1996.[PDF]

    Book Chapters:

• Yan Bai, Yul Chu, M. R. Ito, "On Achieving Efficiency and Fairness in Video Transportation," Springer-Verlag Lecture Notes in Computer Science (LNCS), Vol. 3420/2005, pp. 654-661 (ISBN 3-540-25339-4), the 4^th IEEE/IEE International Conference on Networking (ICN '05), April 2005.
• Yul Chu and M. R. Ito, "Reducing Indirect Mispredictions of Two-Stage Branch Predictors," High Performance Computing Systems and Applications, Chapter 14, pp. 187-206, Kluwer Academic Publishers, 2002.

    Posters/Abstracts:

• Amit Uppal and Yul Chu, "A Dynamic Packet Buffer Management for a Protocol Processor in a Network Interface Card," 2006 US-Korea Conference (UKC2006), Teaneck, New Jersey, Aug. 10-13, 2006.
• Saibhushan Musalappa, Shivakumar Sundaram, Yul Chu, "Energy Savings for Data Caches: ELRU-SEQ Replacement Policy," the 24^th IEEE International Performance Computing and Communications Conference (IPCCC2005) Poster, Phoenix, Arizona, April 7-9, 2005.

    Ph.D. Dissertation

• Cache and Branch Prediction Improvements for Advanced Computer Architecture, Ph.D. Dissertation, Electrical and Computer Engineering, University of British Columbia, May 2001.

    Master's Thesis

• Parallel solution of Sparse Matrix Equation in SPICE on a Transputer Array, M.S. Project Report, Washington State University, July 1995.

   Presentations:

• "Packet Buffer Management for a High-Speed Network Interface," presented at the IEEE International Conference on Computer Communications and Networks (ICCCN2007), Honolulu, Hawaii USA, August 13-16, 2007.
• "A Shared-Memory Packet Buffer Management," presented at the the 9^th Asia-Pacific Network Operations and Management Symposium (APNOMS 2006), Busan, Korea, September 27-29, 2006.
• "A Dynamic Packet Buffer Management for a Protocol Processor in a Network Interface Card," presented at the 2006 US-Korea Conference (UKC2006), Teaneck, New Jersey, Aug. 10-13, 2006.
• "A Class Project for Low-Power Cache Memory Architecture," presented at the 2006 ASEE Annual Conference & Exposition, Computers in Education Division, Chicago, IL, June 18-21, 2006.
•  "A Case for Dual-Mapping One-Way Caches," presented at the IEEE/ACM/IFIP Architecture of Computing Systems (ARCS'06), Frankfurt/Main, Germany, March 13-16, 2006.
•  "A DCT (Design, Code, Test) Project for Instruction Set Architecture," presented at the 5^th IEEE International Conference on Advanced Learning Technologies (ICALT 2005, 3-page short paper), Kaohsiung, Taiwan, July 5-8, 2005.
•  "An Enhanced Dynamic Packet Buffer management," presented at the10^th IEEE Symposium on Computers and Communications (ISCC 2005), La Manga del Mar Menor, Cartagena, Spain, June 27-30, 2005.
•  "An Efficient Indirect Branch Predictor," presented at the ACM 7^th International European Conference on Parallel Computing (Euro-Par 2001), Manchester, United Kingdom, August 28-31, 2001.
•  "The GoStay Predictor: One-Bit Associated Predictor for Reducing Indirect Branch Mispredictions," presented at the 14^th Annual International Symposium on High Performance Computing Systems and Applications (HPCS2000), Victoria, Canada, June 2000.