Publications
Journal papers
  1. P.Zhao, J. McNeely, P.K.Golconda, S. Venigalla, Nan Wang, M.Bayoumi, W.Kuang, R. Barcenas, "Low power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems," submitted to IEEE Trans. on VLSI systems.
  2. Weidong Kuang, P. Zhao, J.S.Yuan, and R. DeMara, "Design of asynchronous circuits for high soft error tolerance in deep submicron CMOS circuits," submitted to IEEE Trans. on VLSI systems.
  3. Weidong Kuang, Lizhi Cao, C.Yu, and J.S.Yuan, "PMOS breakdown effects on digital circuits -- modeling and analysis," accepted by Microelectronics Reliability Journal of Elsevier ( a special issue).
  4. Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy Bayoumi, Robert.A. Barcenas, Weidong Kuang, "Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop," IEEE Trans. on VLSI systems, vol. 15, no.3, 2007, pp.338-345.
  5. W. Kuang, and J. S. Yuan, “Energy-efficient self-timed circuit design using supply voltage scaling,” IEE Proceedings Circuits, Devices and Systems, Vol. 151, no.4, August 2004, pp.278-284.
  6. J. S. Yuan, and W. Kuang, “Teaching Asynchronous Design in Digital Integrated  Circuits,” IEEE Trans. Education, Vol.47, No.3, 2004, pp. 397-404.
  7. W. Kuang, J. S. Yuan, R. Demara, M.Hagedorn, and K. Fant, “Performance analysis and optimization of NCL self-timed rings,” IEE Proceedings Circuits, Devices and Systems, Vol.150, no.3, June 2003, pp.167-172.
  8. Weidong Kuang, “An approach to direct digital sampling of IF bandpass signal and its hardware implementation,” Journal of System Engineering and Electronics, vol. 18, no. 11, November 1996, pp.49-54.

Conference papers

  1. Weidong Kuang, Lizhi Cao, C.Yu, and J.S.Yuan, "PMOS breakdown effects on digital circuits -- modeling and analysis," 19th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis ( ESREF 2008, Netherlands).
  2. W.Kuang, Casto Manuel Ibarra, Peiyi Zhao, "Soft Error Hardening for Asynchronous Circuits," the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, Rome, Italy, Sept., 2007.
  3. Weidong Kuang, Enjun Xiao, Casto Manuel Ibarra, Peiyi Zhao, "Design Asynchronous Circuits for Soft Error Tolerance," IEEE International Conf. on Integrated Circuit Design and Technology, Austin, Texas, June, 2007.
  4. Peiyi Zhao, Jason McNeely, Golconda Pradep, Magdy Bayoumi, Kuang Weidong, "A Low Power Domino with Differential Controlled Keeper," IEEE International Symposium on Circuits and Systems, May 27-30, 2007.
  5. W. Kuang and Peiyi Zhao, "Fault Models for Threshold Logic Circuits Based on Resonant Tunneling Diodes," North Atlantic Test Workshop 2006.

  6. W. Kuang and E. Banatoski, "Testing for Threshold Logic Circuits Based on Resonant Tunneling Diodes," the 6th IEEE Conference on Nanotechnology, Cincinnati Ohio, July 2006.

  7. W. Kuang, J. S. Yuan and A. Ejnioui, "Supply Voltage Scalable System Design Using Self-Timed Circuits," IEEE Computer Society Annual Symposium on VLSI, February 20-21, 2003, Tampa/Clearwater, FL, USA.
  8. W. Kuang and J. S. Yuan, “An adaptive supply-voltage scheme for low power self-timed CMOS digital design,” Proceedings of the 16th International Conference on VLSI Design, January 4-8, 2003, New Delhi, India.
  9. Weidong Kuang and Jiann S. Yuan, “Soft digital signal processing using self-timed circuits,” IEEE International Conference on Semiconductor Electronics, December 19-21, 2002, Pennang, Malaysia.
  10. W. Kuang and J. S. Yuan, “Low power operation using self-timed circuits and ultra-low supply voltage,” The 14th IEEE International Conference on Microelectronics, December 11-13, 2002, Beirut, Lebanon.
  11. W. Kuang, J.S. Yuan, R. Demara, D. Ferguson, and M. Hagedorn, “A delay insensitive FIR filter for DSP applications,” NASA 9th Symposium on VLSI Design, Albuquerque, New Mexico, November 8-9, 2000.
  12. Weidong Kuang and Jieping Zhang, " Track techniques in a solid state phased array radar," Proceedings of the 3rd Annual Symposium of Beijing Society of Astronautics, China, Sept. 1997, pp. 61-64. (in Chinese)
  13. Qiwu Tan and Weidong Kuang, “Detecting the amplitude and phase of multi-channel for phased array,” International Symposium on Antenna and Electromagnetics, August 1997, Xi’an, China, pp. 300-305.
  14. Weidong Kuang, "Analysis of the effect of SAR autofocus error on imaging performance," The Symposium on Radar Target Imaging, Beijing, China, pp. 35-38, 1995. (in Chinese)

Technical reports for industry

  1. Weidong Kuang, “Floating-point using NCL: rounding and division,” technical report presented at Theseus Logic, Inc. on April 26, 2001.
  2. Weidong Kuang, “Floating-point using NCL: analysis and optimization for NCL rings,” technical report presented at Theseus Logic, Inc. on July 2, 2001.
  3. Weidong Kuang, “NCL applications,” power-point slides presented at Theseus Logic, Inc. on November 14, 2001.

Dissertation and thesis

  1. Ph.D. Dissertation, “Iterative ring and power-aware design techniques for self-timed digital circuits,” department of electrical and computer engineering, University of Central Florida, August, 2003.
  2. M.S. Thesis, “Study of IF bandpass signal sampling and its hardware implementations”, department of electrical engineering, Best Thesis Award at Nanjing University of Aeronautics and Astronautics, 1994.

Special Talks

  1.  "Communication: an electronic technology perspective", Feb 26, 2008, UTPA, Department of Communication, COM1315